1. Field of the Invention
The invention relates to a circuit configuration for synchronizing pulse-shaped signals, having a clock-controlled flip-flop with a data input, a data output and a clock input, the pulse-shaped signal to be synchronized is supplied to the data input of the flip-flop, and the synchronized signal can be picked up at the data output of the flip-flop.
2. Description of the Related Art
Such a circuit configuration for synchronizing asynchronous pulse-shaped signals is known, for instance, from the book entitled Halbleiter-Schaltungstechnik [Semiconductor Circuitry], by Tietze and Schenk, 8th edition, pages 255-256, in particular FIG. 10.49 thereof. In that case, the asynchronous signal is supplied to the data input of a clock-controlled flip-flop. The system clock pulse with which synchronizing is to be carried out is present at the clock input of the flip-flop. The synchronized data signal can then be picked up at the data output of the flip-flop. The asynchronous signal is weighted with the leading and/or trailing edge of the system pulse. In digital circuits, such as large scale integrated MOS circuits, slow phase shifts sometimes occur between the system clock signals of a signal-transmitting circuit and those of a signal-processing circuit. Usually, such shifts can be ascribed to thermal effects. If a leading or trailing edge of the data signal is located at the input of the signal-processing circuit at the instant of weighting by its system clock pulse, the result is weighting uncertainty, which leads to jittering having the width of one clock period.
It is accordingly an object of the invention to provide a synchronization circuit configuration, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and which improves a circuit configuration for synchronizing pulse-shaped signals in such a way that it assures jitter-free synchronization.